1. Technical Field
Various embodiments relate generally to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device including a pipe gate and a method of manufacturing the same.
2. Related Art
A non-volatile memory device can retain data stored therein even in the absence of a power supply. Because creating two-dimensional memory devices that have memory cells fabricated in the form of a single layer on silicon substrates is reaching a limitation in regards to integration, suggestions of three-dimensional structured non-volatile memory devices that have memory cells vertically stacked on silicon substrates have been proposed.
The structure and features of a conventional three-dimensional (3-D) non-volatile memory device are described with reference to FIG. 1.
FIG. 1 is a perspective view illustrating the structure of a conventional 3-D non-volatile memory device. For illustration purposes, interlayer insulating layers are not depicted.
As illustrated in FIG. 1, the conventional 3-D non-volatile memory device may include channel layers CH. Each of the channel layers CH may include a pipe channel layer P_CH formed on a pipe gate PG and a pair of vertical channel layers V_CH coupled to the pipe channel layer P_CH. Each of the channel layers CH may be surrounded by a memory layer (not illustrated). The memory layer may include a tunnel insulating layer, a charge trap layer and a charge blocking layer.
In addition, the memory device may include stacked word lines WL that surround the vertical channel layers V_CH, a source select line SSL and a drain select line DSL each stacked above the word lines WL, a source line SL, and bit lines BL.
One drawback for the conventional 3-D non-volatile memory device is that, when a slit is formed in order to separate a source side word line and a drain side word line from each other, a pipe channel layer P_CH and the memory layer that surround the pipe channel layer P_CH may be damaged.
In addition, the memory layer surrounding the pipe channel layer P_CH may be configured to be used as a gate insulating layer of a pipe transistor, and if it is not thick enough to function as a gate insulating layer, charges may be trapped in the charge trap layer during a program or erase operation, thereby varying the threshold voltage of the pipe transistor.